1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an in-plane switching (IPS) mode LCD device and a fabricating method thereof.
2. Discussion of the Related Art
Generally, a conventional liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal (LC) molecules. The LC molecules have a definite orientational order in alignment resulting from their thin and long shapes. The alignment direction of the LC molecules can be controlled by applying an electric field to the LC molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the LC molecules also changes. Since the incident light is refracted to the orientation of the LC molecules due to the optical anisotropy of the aligned LC molecules, images are displayed.
Of the different types of known LCDs, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, are the subject of significant research and development because of their high resolution and superiority in displaying moving images.
FIG. 1 is a schematic plan view of an array substrate for a conventional IPS mode LCD device.
In FIG. 1, a gate line 12 and a common line 16 are disposed on a substrate 10 and spaced apart from each other. A data line 24 that defines a pixel region “P” with the gate line 12 crosses the gate line 12 and the common line 16. A thin film transistor “T” including a gate electrode 14, an active layer 20, source and drain electrodes 26 and 28 is disposed at a crossing of the gate line 12 and the data line 24. The gate electrode 14 is connected to the gate line 12 and the source electrode 26 is connected to the data line 24.
A pixel electrode 30 connected to the drain electrode 28 and a common electrode 17 connected to the common line 16 are disposed at the pixel region “P.” The pixel electrode 30 is composed of an extended portion 30a, a plurality of vertical portions 30b and a horizontal portion 30c. The extended portion 30a is extended from the drain electrode 28. The plurality of vertical portions 30b are extended from the extended portion 30a and spaced apart from each other. The horizontal portion 30c combines the plurality of vertical portions 30b. On the other hand, the common electrode 17 is composed of a horizontal portion 17a and a plurality of vertical portions 17b. The horizontal portion 17a combines the plurality of vertical portions 17b. The plurality of vertical portions 17b extended from the common line 16 are alternately disposed with the plurality of vertical portions 30b and spaced apart from the data line 24.
Furthermore, a storage capacitor “C” is disposed adjacent to the pixel region “P.” The storage capacitor “C” includes the gate line 12 and the common line 16 as a first storage electrode, and a transparent electrode 36 as a second storage electrode. A gate insulating layer and a passivation layer having a low dielectric constant (not shown) are interposed between the first and second storage electrodes.
FIGS. 2A to 2D are schematic cross-sectional views taken along a line II—II of FIG. 1, which show a fabricating process of an array substrate for a conventional IPS mode LCD device.
In FIG. 2A, after one of the conductive metal group including aluminum (Al), aluminum alloy such as aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) and tungsten (W) is deposited on a substrate 10, a gate line 12 including a gate electrode 14, a common line 16 spaced apart from the gate line 12 and a common electrode 17 (of FIG. 1) including a horizontal portion 17a and a plurality of vertical portions 17b (of FIG. 1) are formed through a first mask process. The plurality of vertical portions 17b (of FIG. 1) are perpendicularly extended from the common line 16 and the horizontal portions 17a combines the plurality of vertical portions 17b (of FIG. 1). Next, a gate insulating layer 18 is formed on an entire surface of the substrate 10 by depositing one of the inorganic insulating material group including silicon nitride (SiNx) and silicon oxide (SiO2). After an amorphous silicon (a-Si:H) and an impurity-doped amorphous silicon (n+a-Si:H) are deposited on the gate insulator 18, an active layer 20 and an ohmic contact layer 22 of an island shape are formed through a second mask process.
In FIG. 2B, after one of the conductive metal group including aluminum (Al), aluminum alloy such as aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) and tungsten (W) is deposited on an entire surface of the substrate 10, a data line 24 defining a pixel region “P” with the gate line 12, source and drain electrodes 26 and 28 spaced apart from each other, and a pixel electrode 30 including an extended portion 30a (of FIG. 1), a plurality of vertical portions 30b and a horizontal portion 30c are formed through a third mask process. The horizontal portion 30c overlaps the common line 16 partially. The active layer 20 between the source and drain electrodes 26 and 28 is exposed through etching the ohmic contact layer 22 by using the source and drain electrodes 26 and 28 as a mask.
In FIG. 2C, after one of the organic insulating material group including benzocyclobutene (BCB) and acrylic resin is deposited on an entire surface of the substrate 10, a passivation layer 32 having a contact hole 34 exposing the horizontal portion 30c is formed through a fourth mask process.
In FIG. 2D, after one of the transparent conductive metal group including indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on an entire surface of the substrate 10, a transparent electrode 36 contacting the horizontal portion 30c through the contact hole 34 is formed over the gate line 12 and the common line 16 through a fifth mask process. Both the gate line 12 and the common line 16 function as a first storage electrode of a storage capacitor “C” and the transparent electrode 36 functions as a second storage electrode of the storage capacitor “C.”
In the structure of FIG. 1, since the data line 24 and the adjacent vertical portion 17b are spaced apart from each other, liquid crystal molecules between the data line 24 and the adjacent vertical portion 17b are undesirably aligned due to signal interference between the common line 17 and the data line 24 so that light leakage phenomenon can occur. Accordingly, the display quality of a liquid crystal panel is deteriorated.
Moreover, the horizontal portion 30c only partially overlaps the common line 16, and the additional transparent electrode 36 is formed over the gate line 12 and the common line 16 to form the storage capacitor “C.” The horizontal portion 30c is not extended over the entire common line 16 and the gate line 12 because the gate insulating layer of SiNx or SiO2 cannot prevent signal interference between the horizontal portion 30c and the common and gate lines 16 and 12. If the horizontal portion 30c is extended over the common line 16 and the gate line 12, signals of the common line 16 and the gate line 12 may influence the pixel electrode 30 (of FIG. 1) through the horizontal portion 30c. Therefore, the overlapping portion between the first horizontal portion 30c and the common line 16 should be minimized.
However, the capacitance of the storage capacitor “C” also decreases according to the minimization of the overlapping portion. To solve this problem, the additional transparent electrode 36 connected to the horizontal portion 30c is formed over the common line 16 and the gate line 12. Accordingly, the area of the storage capacitor “C” increases so that enough capacitance can be obtained. Furthermore, since the transparent electrode 36 is electrically connected to the pixel electrode 30 (of FIG. 1), the transparent electrode 36 can be used as a pad when the TFT characteristics are inspected. However, fabrication cost increases and production yield decreases due to the additional process for the transparent electrode 36.